Various systems and circuits require controlling the duty cycle of a clock signal. For example, some processor-based systems need a clock signal to have a duty cycle of 50%. The duty cycle of 50% may be necessary for accurate control over critical timing margins. However, due to effects from distortion and skewing, a clock signal may have an undesired duty cycle much higher or lower than 50%. Other systems employ pulse-width modulation and require generating digital signals with varying duty cycles. Therefore, it is important to have the ability to manipulate the duty cycle of a digital signal. In addition, it is sometimes important to generate a desired duty cycle quickly, without long delay periods.
Delay-locked loops (DLLs) and phase-locked loops (PLLs) are two techniques for accomplishing a desired clock signal. A DLL can be used to synchronize two clock signals of the same frequency by delaying one of the signals until the phases of the two clock signals are aligned. A phase detector is used to determine the appropriate delay of one clock signal and a delay element delays the clock signal until the two signals are in phase, or locked. As the name suggests, the DLL locks phase only and the duty cycle is not necessarily locked, particularly in the presence of process variations. Therefore, what is needed is a low-latency circuit and method for adjusting the duty cycle of a clock signal without necessarily relying on DLLs or PLLs.